1. Field of the Invention
The present invention relates to data processing apparatus, and in particular to techniques for improving the flexibility with which such data processing apparatus can be configured during use.
2. Description of the Prior Art
It is known to provide a data processing apparatus having a plurality of logic elements for processing data, and a plurality of connections via which data is passed between those logic elements. Typically, a clock signal will be used to control the operation of the logic elements within the apparatus, and to control the transfer of signals between those logic elements. When designing such an apparatus, regard will usually be taken of the target clock speed, i.e. operating frequency, that the apparatus will need to run at, since this will ultimately limit how much processing a particular logic element can perform in a single clock cycle, and how far a signal may pass along a connection in each clock cycle.
Having regard to the issue of transferring signals over connections, the designer may decide, having regard to the target clock speed, that it is appropriate to add one or more storage elements along the path of a particular connection, in order to separate that connection into one or more path portions. In any one clock cycle, the signal then only needs to traverse the length of each path portion.
It will be appreciated that whilst the addition of such a storage element may be necessary having regard to a particular target operating frequency, it is undesirable to add more storage elements than are actually required, as this will have an impact on processing speed, since it will increase the number of clock cycles taken for a signal to traverse a particular connection.
Although an apparatus will be designed having regard to a target clock speed, it is often the case that any particular piece of apparatus produced in accordance with that design will not necessarily always be required to operate at that target clock speed. For example, it is known to provide standby modes of operation in which the clock speed is reduced in order to reduce power consumption. Since the apparatus was designed for the target clock speed, it will not necessarily be operating as efficiently when operating at a different clock speed. For example, signals may be temporarily stored in storage elements when in fact they could have been propagated further through the connection given the lower clock speed.
It will also be appreciated that there are other operating conditions that may change, such as the use of different voltage levels in different modes of operation, and in addition the speed of operation of the apparatus may vary in accordance with the operating environment of the apparatus, for example whether the surrounding environment is warm or cold, etc. Additionally, it will be appreciated that due to manufacturing tolerances, each apparatus produced in accordance with a design will not be absolutely identical in its operational characteristics. All of these issues can result in the apparatus operating sub-optimally, in that the design of the apparatus will have taken into account a worst case set of operating characteristics (e.g. clock speed, operating voltage, etc), and this will not always match the actual operational characteristics of any particular apparatus produced in accordance with the design.
Accordingly, it would be desirable to provide an improved data processing apparatus which could adapt to such different operating conditions.